1. Field of the Invention
The present invention relates generally to semiconductor device assemblies, or so-called “multi-chip modules,” and, more specifically, to multi-chip modules in which two or more semiconductor devices are stacked relative to one another. In particular, the present invention relates to stacked semiconductor device assemblies in which the distances between adjacent, stacked semiconductor devices are determined, at least in part, by a plurality of discrete spacers interposed therebetween, and discrete conductive elements protrude from a central region of the lower semiconductor device and pass through a common aperture formed between the active surface of the lower semiconductor device, the back side of the upper semiconductor device and two of the spacers.
2. Background of Related Art
In order to conserve the amount of surface area, or “real estate,” consumed on a carrier substrate, such as a circuit board, by semiconductor devices connected thereto, various types of increased density packages have been developed. Among these various types of packages is the so-called “multi-chip module” (MCM). Some types of multi-chip modules include assemblies of semiconductor devices that are stacked one on top of another. The amount of surface area on a carrier substrate that may be saved by stacking semiconductor devices is readily apparent—a stack of semiconductor devices consumes roughly the same amount of real estate on a carrier substrate as a single, horizontally oriented semiconductor device or semiconductor device package.
Due to the disparity in processes that are used to form different types of semiconductor devices (e.g., the number and order of various process steps), the incorporation of different types of functionality into a single semiconductor device has proven very difficult to actually reduce to practice. Even in cases where semiconductor devices that carry out multiple functions can be fabricated, multi-chip modules that include semiconductor devices with differing functions (e.g., memory, processing capabilities, etc.) are often much more desirable since the separate semiconductor devices may be fabricated independently and later assembled with one another much more quickly and cost-effectively (e.g., lower production costs due to higher volumes and lower failure rates).
Multi-chip modules may also contain a number of semiconductor devices that perform the same function, effectively combining the functionality of all of the semiconductor devices thereof into a single package.
An example of a conventional, stacked multi-chip module includes a carrier substrate, a first, larger semiconductor device secured to the carrier substrate, and a second, smaller semiconductor device positioned over and secured to the first semiconductor device. The second semiconductor device does not overlie bond pads of the first semiconductor device and, thus, the second semiconductor device does not cover bond wires that electrically connect bond pads of the first semiconductor device to corresponding contacts or terminals of the carrier substrate. As the bond pads of each lower semiconductor device are not covered by the next higher semiconductor device, vertical spacing between the semiconductor devices is not required. Thus, any suitable adhesive may be used to secure the semiconductor devices to one another. Such a multi-chip module is disclosed and illustrated in U.S. Pat. No. 6,212,767, issued to Tandy on Apr. 10, 2001 (hereinafter “the '767 Patent”). Notably, since the sizes of the semiconductor devices of such a multi-chip module must continue to decrease as they are positioned increasingly higher in the stack, the obtainable heights of such multi-chip modules and the number of semiconductor devices that may be placed therein is severely limited.
Another example of a conventional multi-chip module is described in U.S. Pat. No. 5,323,060, issued to Fogal et al. on Jun. 21, 1994 (hereinafter “the '060 Patent”). The multi-chip module of the '060 Patent includes a carrier substrate with semiconductor devices disposed thereon in a stacked arrangement. The individual semiconductor devices of each multi-chip module may be the same size or different sizes, with upper semiconductor devices being either smaller or larger than underlying semiconductor devices. Adjacent semiconductor devices of each of the multi-chip modules disclosed in the '060 Patent are secured to one another with an adhesive layer. The thickness of each adhesive layer well exceeds the loop heights of wire bonds protruding from a semiconductor device upon which that adhesive layer is to be positioned. Accordingly, the presence of each adhesive layer prevents the back side of an overlying, upper semiconductor device from contacting bond wires that protrude from an immediately underlying, lower semiconductor device of the multi-chip module. The adhesive layers of the multi-chip modules disclosed in the '060 Patent do not encapsulate or otherwise cover any portion of the bond wires that protrude from any of the lower semiconductor devices. It does not appear that the inventors named on the '060 Patent were concerned with overall stack heights. Thus, the multi-chip modules of the '060 Patent may be undesirably thick due to the use of thick spacers or adhesive structures between each adjacent pair of semiconductor devices, resulting in wasted adhesive and excessive stack height.
A similar but more compact multi-chip module is disclosed in U.S. Pat. No. Re. 36,613, issued to Ball on Mar. 14, 2000 (hereinafter “the '613 Patent”). The multi-chip module of the '613 Patent includes many of the same features as those disclosed in the '060 Patent, including adhesive layers of carefully controlled thicknesses that space vertically adjacent semiconductor devices apart a greater distance than the loop heights of wire bonds protruding from the lower of the adjacent dice. The use of thinner bond wires with low-loop profile wire bonding techniques permits adjacent semiconductor devices of the multi-chip module disclosed in the '060 Patent to be positioned more closely to one another than adjacent semiconductor devices of the multi-chip modules disclosed in the '060 Patent. Nonetheless, an undesirably large amount of additional space may remain between the tops of the bond wires protruding from one semiconductor device and the back side of the next higher semiconductor device of such a stacked multi-chip module.
The vertical distance that adjacent semiconductor devices of a stacked type multi-chip module are spaced apart from one another may be reduced by arranging the immediately underlying semiconductor devices, such that upper semiconductor devices are not positioned over bond pads of immediately lower semiconductor devices or bond wires protruding therefrom. Thus, adjacent semiconductor devices may be spaced apart from one another a distance that is about the same as or less than the loop heights of the wire bonds that protrude above the active surface of the lower semiconductor device. U.S. Pat. No. 6,051,886, issued to Fogal et al. on Apr. 18, 2000 (hereinafter “the '886 Patent”), discloses such a multi-chip module. According to the '886 Patent, wire bonding is not conducted until all of the semiconductor devices of such a multi-chip module have been assembled with one another and with the underlying carrier substrate. The semiconductor devices of the multi-chip modules disclosed in the '886 Patent must have bond pads that are arranged on opposite peripheral edges. Semiconductor devices with bond pads positioned adjacent the entire peripheries thereof could not be used in the multi-chip modules of the '886 Patent. This is a particularly undesirable limitation due to the ever-increasing feature density of state-of-the-art semiconductor devices, which is often accompanied by a subsequent need for an ever-increasing number of bond pads on semiconductor devices.
Conventionally, when a particular amount of spacing is needed between semiconductor devices to separate discrete conductive elements, such as bond wires, that protrude above an active surface of one semiconductor device from the back side of the next higher semiconductor device, the semiconductor devices of stacked multi-chip modules have been separated from one another with preformed spacers. Exemplary spacers that have been used in stacked semiconductor device arrangements have been formed from dielectric-coated silicon (which may be cut from scrapped dice) or a polyimide film. An adhesive material typically secures such a spacer between adjacent semiconductor devices. The use of such preformed spacers is somewhat undesirable since an additional alignment and assembly step is required for each such spacers. If silicon spacers are employed, an adhesive must be applied to both surfaces thereof, and prior passivation of the spacer surfaces may be required to prevent shorting between two adjacent devices. Proper alignment of a preformed spacer with a semiconductor device requires that a spacer not be positioned over bond pads of the semiconductor device.
Another example of a conventional MCM is disclosed in U.S. Pat. No. 6,569,709 to Derderian (hereinafter “the '709 Patent”), the disclosure of which is incorporated in its entirety by reference herein. More specifically, the '709 Patent discloses, as shown in FIG. 1 hereof, a conventional assembly 10 including a substrate 20 with two semiconductor devices 30A, 30B (collectively referred to as “semiconductor devices 30”) positioned thereover in stacked arrangement.
The depicted substrate 20 of the '709 Patent is an interposer with a number of bond pads, which are referred to herein as contact areas 24, through which electrical signals are input to or output from semiconductor devices 30 carried upon a surface 22 of substrate 20. Each contact area 24 corresponds to a bond pad 34 on an active surface 32 of one of the semiconductor devices 30 positioned upon substrate 20.
A first semiconductor device 30A is secured to substrate 20. Peripherally located bond pads 34 of first semiconductor device 30A communicate with corresponding contact areas 24 of substrate 20 by way of discrete conductive elements 38A. A second semiconductor device 30B is positioned over, or “stacked,” on first semiconductor device 30A. A back side 35 of second semiconductor device 30B is electrically isolated from discrete conductive elements 38A. Second semiconductor device 30B is secured to first semiconductor device 30A by way of an adhesive element 36 interposed between and secured to active surface 32 of first semiconductor device 30A and back side 35 of second semiconductor device 30B. The adhesive element 36 may comprise a thermoplastic resin, a thermoset resin, or an epoxy. The MCM is conventionally covered with a protective encapsulant. Since conventional multi-chip modules may be affixed to one another with a continuous adhesive element with mechanical properties e.g., modulus of elasticity, coefficient of thermal expansion (CTE), etc., which do not precisely correspond to the mechanical properties of the semiconductor devices or encapsulant materials, stresses, such as thermal stresses, may develop between the semiconductor devices. CTE mismatch between the adhesive element and encapsulant material can lead to delamination of components of the assembly and, specifically, of delamination along the interface between a transfer molded encapsulant of the assembly and the mass, or “pillow,” of adhesive element 36.
A further conventional MCM configuration is disclosed in U.S. Pat. No. 6,531,784 to Shim et al. Particularly, in the disclosed “stacked-die” embodiment, a second die has been mounted on top of the first die with elongated spacer strips. Conductive wires are bonded to corresponding terminal pads on the first die, channeled through a corresponding groove in a corresponding spacer strip, then bonded to a corresponding one of the terminal pads on the substrate. The spacer strips serve to captivate the bonding wires and keep them separated from one another and the surfaces of the dice. The elongated shape of the spacer strip increases the surface area contact of the die and spacer, leading to problems from CTE mismatch.
In view of the foregoing, it appears that a method for forming stacked semiconductor device assemblies that reduces the likelihood of damage to semiconductor devices and associated wire bonds, as well as provides flexibility in bond pad number and placement on the semiconductor devices of the assembly, would be useful.